View CS5451A_40317.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

CS5451A
Six-Channel Delta-Sigma Analog-to-Digital Converter
Features
Synchronous Sampling On-chip 1. 2V Reference (25ppm/C typ) Power Supply Configurations:
- VA+ = +3 V; VA- = -2 V; VD+ = +3 V - Supply tolerances 10%
Description
The CS5451A is a highly integrated Delta-Sigma () Analog-to-Digital Converter (ADC) developed for the Power Measurement Industry. The CS5451A combines six ADCs, decimation filters, and a serial interface on a single chip. The CS5451A interfaces directly to a current transformer or shunt to measure current, and resistive divider or transformer to measure voltage. The product features a serial interface for communication with a micro-controller or DSP. The product is initialized and fully functional upon reset, and includes a Voltage Reference.
Power Consumption
- 20 mW Typical at VD+ = +3 V
Simple Four-wire Serial Interface Charge Pump Driver output generates negative power supply. Ground-Referenced Bipolar Inputs
ORDERING INFORMATION: CS5451A-IS -40 C to +85C 28-pin SSOP
VA+ GAIN IIN1+ IIN1VIN1+ VIN14th Order Modulator 4th Order Modulator
RESET
VD+
x1, 20
Decimation Filter
x1
Decimation Filter
IIN2+ IIN2VIN2+ VIN2-
x1, 20
4th Order Modulator
Decimation Filter SE
x1
4th Order Modulator 4th Order Modulator
Decimation Filter Serial Interface
OWRS SDO FSO SCLK
IIN3+ IIN3VIN3+ VIN3VREFIN VREFOUT
x1, 20
Decimation Filter
x1
4th Order Modulator
Decimation Filter
x1
Voltage Reference
Clock
Pulse Output Regulator
CPD
AGND
VA-
XIN
DGND
Preliminary Product Information
http://www.cirrus.com
This document contains information for a new product. Cirrus Logic reserves the right to modify this product without notice.
Copyright Cirrus Logic, Inc. 2003 (All Rights Reserved)
OCT `03 DS635PP1 1
CS5451A
TABLE OF CONTENTS
1. PIN DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2. CHARACTERISTICS AND SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3. GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3.1 Theory of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3.2 Performing Measurements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3.3 High Rate Digital Filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3.4 Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3.5 System Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3.6 Analog Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3.7 Voltage Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3.8 Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.9 PCB Layout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 4. PACKAGE DIMENSIONS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 5. REVISIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
LIST OF FIGURES
Figure 1. Serial Port Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Figure 2. Typical Connection Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Figure 3. Serial Port Data Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Figure 4. Close-up of One Data Frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Figure 5. Generating VA- with a Charge Pump . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2
DS635PP1
CS5451A
1. PIN DESCRIPTION
Serial Clock Output SCLK Serial Data Output SDO Frame Sync FSO Serial Port Enable SE Current Input Gain GAIN Analog Ground AGND Reference Input VREFIN Reference Output VREFOUT Positive Analog Supply VA+ Negative Analog Supply VADifferential Voltage Input 3 VIN3+ Differential Voltage Input 3 VIN3Differential Current Input 3 IIN3+ Differential Current Input 3 IIN31 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15
VD+ DGND CPD XIN RESET OWRS VIN1+ VIN1IIN1+ IIN1VIN2+ VIN2IIN2+ IIN2-
Digital Supply Digital Ground Charge Pump Drive Master Clock Reset Output Word Rate Select Differential Voltage Input 1 Differential Voltage Input 1 Differential Current Input 1 Differential Current Input 1 Differential Voltage Input 2 Differential Voltage Input 2 Differential Current Input 2 Differential Current Input 2
Clock Generator XIN - Master Clock Input Control Pins and Serial Data I/O SE - Serial Port Enable
When SE is low, the output pins of the serial port are 3-stated.
SDO - Serial Port Output
Data will be at a rate determined by SCLK.
FSO - Frame Signal Output
Framing signal output for data transfer from SDO pin.
SCLK - Serial Clock Output
A clock signal on this pin determines the output rate of data for SDO pin. Rate of SCLK is determined by XIN frequency and state of OWRS input pin.
RESET - Reset
When reset is taken low, all internal registers are set to their default states.
GAIN - Input Gain Control
Sets input gain for current channels. A logic high sets internal gain to 1, a logic low level sets the gain to 20. If no connection is made to this pin, it will default to logic low level (through internal 200 k resistor to DGND).
OWRS - Output Word Rate Select
When OWRS is set to logic low, the output word rate (OWR) at SDO pin is XIN/2048 (Hz). When set to logic high, the OWR at SDO pin is XIN/1024 (Hz). If no connection is made to this pin, then OWRS will default to logic low level (through internal 200 k resistor to DGND).
DS635PP1
3
CS5451A
Measurement and Reference Input IIN(1-3)+, IIN(1-3)- - Differential Current Inputs
Differential analog input pins for current channels.
VIN(1-3)+, VIN(1-3)- - Differential Voltage Inputs
Differential analog input pins for voltage channels.
VREFOUT - Voltage Reference Output
The on-chip voltage reference is output from this pin. The voltage reference has a nominal magnitude of 1.2 V and is referenced to the AGND pin on the converter.
VREFIN - Voltage Reference Input
The voltage input to this pin establishes the voltage reference for the on-chip modulator.
Power Supply Connections VA+ - Positive Analog Supply
The positive analog supply is nominally +3V 10% relative to AGND.
VA- - Negative Analog Supply
The negative analog supply is nominally - 2V 10% relative to AGND.
AGND - Analog Ground
The analog ground pin for input signals.
VD+ - Positive Digital Supply
The positive digital supply is nominally +3V 10% relative to DGND.
DGND - Digital Ground
The digital ground is typically at the same level as AGND.
CPD - Charge Pump Drive
This output pin drives the external charge pump circuitry to create a negative supply voltage.
4
DS635PP1
CS5451A
2.
* * *
CHARACTERISTICS AND SPECIFICATIONS
Min / Max characteristics and specifications are guaranteed over all Operating Conditions Typical characteristics and specifications are measured at nominal supply voltages and TA = 25 C. DGND = 0 V. All Voltages with respect to 0V.
ANALOG CHARACTERISTICS
Parameter Symbol THD (DC, 50, 60 Hz) CMRR Min 74 80 VAGain=20 Gain=1 Gain=20 Gain=1 (50, 60 Hz) Gain = 20 Gain = 1 (Note 2) Gain=20 Gain=1 Gain=20 Gain=1 Gain=20 Gain=1 Gain=20 Gain=1 OWRS = "0" OWRS = "1" OWR OWR IC IC EII EII VIN VIN VOS VOS 50 Typ XIN/4 80 1.6 0.500 10 500 XIN/2048 XIN/1024 Max VA+ 1 20 -120 20 1 600 1 20 2.5 50 3.75 75 Unit dB dB V Hz mVP-P VP-P mV mV dB pF pF k k
Vrms Vrms Vrms Vrms Vrms Vrms
Accuracy (All Channels)
Total Harmonic Distortion Common Mode Rejection Common Mode + Signal on Input Input Sampling Rate
Analog Inputs(Note 1)
Differential Input Voltage Range [(IIN+) - (IIN-)] or [(VIN+) - (VIN-)] Bipolar Offset Crosstalk (Channel-to-Channel) Input Capacitance Effective Input Impedance
Noise (Referred to Input) 0-60 Hz 0-1 kHz 0-2 kHz
Dynamic Characteristics
High Rate Filter Output Word Rate Hz Hz
Notes: 1. All "Gain = 20" specifications apply only to the Current Channels. Voltage Channels are set to Gain=1. 2. Effective Input Impedance (EII) varies with clock frequency (XIN) and Input Capacitance (IC) EII = 1/(IC*XIN/4)
DS635PP1
5
CS5451A
ANALOG CHARACTERISITCS
Parameter (continued) Symbol REFOUT (Output Current 1 A Source or Sink) VR PSRR VREF+ Min 1.15 60 1.15 IA+ ID+ (Note 3) (DC) (50, 60 Hz) PSCA PSCD PC PSRR PSRR 50 60 Typ 25 6 1.2 Max 1.25 50 10 1.25 10 1 3 4 27 Unit V ppm/C mV dB V pF A mA mA mW dB dB
Reference Output
Output Voltage Temperature Coefficient Load Regulation Power Supply Rejection
Reference Input Input Voltage Range
Input Capacitance Input CVF Current
Power Supplies Power Supply Currents
Power Consumption Power Supply Rejection (see Note 4)
Notes: 3. All outputs unloaded. All inputs CMOS level. 4. Definition for PSRR: VREFIN tied to VREFOUT, VA+ = VD+ = 3V, AGND = DGND = 0V, VA- = - 2V (using charge-pump circuit with CPD). In addition, a 106.0 7mV rms (60 Hz) sinewave is imposed onto the VA+ and VD+ pins. The "+" and "-" input pins of both input channels are shorted to VA-. 2048 instantaneous digital output data words are collected for the channel under test. The rms value of the digital sinusoidal output signal is calculated, and this rms value is converted into the rms value of the sinusoidal voltage (measured in mV) that would need to be applied at the channel's inputs, in order to cause the same digital sinusoidal output. This voltage is then defined as Veq. PSRR is then (in dB):
106.07 PSRR = 20 log --------------- V eq
DIGITAL CHARACTERISTICS (See Note 5)
Parameter High-Level Input Voltage Low-Level Input Voltage High-Level Output Voltage Low-Level Output Voltage Input Leakage Current 3-State Leakage Current Digital Output Pin Capacitance Notes: 5. All measurements performed under static conditions. 6. For OWRS and GAIN pins, input leakage current is 30 A (Max). Iout = -5.0 mA Iout = 5.0 mA (Note 6) Symbol VIH VIL VOH VOL Iin IOZ Cout Min 0.6 VD+ 0.0 (VD+) - 1.0 Typ 1 9 Max VD+ 0.8 0.4 10 10 Unit V V V V A A pF
6
DS635PP1
CS5451A
RECOMMENDED OPERATING CONDITIONS
Parameter DC Power Supplies Positive Digital Positive Analog Negative Analog Symbol VD+ VA+ VAVREF+ Min 2.7 2.7 -2.2 Typ 3.0 3.0 -2.0 1.2 Max 3.5 3.5 -1.8 Unit V V V V
Voltage Reference Input
ABSOLUTE MAXIMUM RATINGS
Parameter DC Power Supplies Positive Digital Positive Analog Negative Analog (Note 7 and 8) (Note 9) All Analog Pins All Digital Pins Symbol VD+ VA+ VAIIN IOUT PDN VINA VIND TA Tstg Min -0.3 -0.3 -2.5 (VA-) - 0.3 -0.3 -40 -65 Typ Max +3.5 +3.5 -0.3 10 25 500 (VA+) + 0.3 (VD+) + 0.3 85 150 Unit V V V mA mA mW V V C C
Input Current, Any Pin Except Supplies Output Current Power Dissipation Analog Input Voltage Digital Input Voltage Ambient Operating Temperature Storage Temperature
Notes: 7. Applies to all pins including continuous over-voltage conditions at the analog input (AIN) pins. 8. Transient current of up to 100 mA will not cause SCR latch-up. Maximum input current for a power supply pin is 50 mA. 9. Total power dissipation, including all input currents and output currents. WARNING: Operation at or beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes.
DS635PP1
7
CS5451A
SWITCHING CHARACTERISTICS
Parameter Master Clock Frequency Master Clock Duty Cycle Rise Times Fall Times Any Digital Input (Note 11) Any Digital Output Any Digital Input (Note 11) Any Digital Output (Note 10) OWRS = "0" OWRS = "1" Pulse Width High (Note 10) Pulse Width Low (Note 10) (Note 10) (Note 10) (Note 10) Symbol XIN trise tfall Min 3 40 Typ 4.000 50 50 Max 5 60 1.0 1.0 Unit MHz % s ns s ns
Serial Port Timing Serial Clock Frequency
SCLK SCLK t1 t2 t3 t4 t5 t6 t7
-
500 1000 0.5 0.5 0.5 1 -
50 50 50
kHz kHz SCLK SCLK ns SCLK SCLK ns ns
Serial Clock SCLK falling to New Data Bit
FSO Falling to SCLK Rising Delay FSO Pulse Width SE Rising to Output Enabled SE Falling to Output in Tri-state
Notes: 10. Device parameters are specified with a 4. 000MHz clock, OWRS = 1. 11. Specified using 10% and 90% points on wave-form of interest. Output loaded wi th 50pF.
S DO
MSB(V1)
MSB(V1) - 1
LSB(I3)
t3 S CLK t FS O t
5
4
t1
t2
t SE
6
t
6
Figure 1. Serial Port Timing
8
DS635PP1
CS5451A
3. GENERAL DESCRIPTION
The CS5451A is designed for 3-phase power meter applications and interfaces to a current transformers or shunt to measure current, and a resistive divider or transformer to measure voltage. The CS5451A combines six modulators and decimation filters, three channels assigned for current input that have programmable input gain amplifiers, and three channels assigned for voltage input. The CS5451A includes six decimation filters that output data at a 2000 Hz or 4000 Hz output word rate (OWR) when the input frequency at XIN = 4.096 MHz. The device outputs data on a serial output port.
3.1
Theory of Operation
The CS5451A is designed to operate from a single +3V supply and provides a 8 0mV P-P and 1. 6VP-P input range for the current channels and 1.6 VP-P range for the voltage channels. These voltages represent the maximum zero-to-peak voltage levels that can be presented to the inputs. The CS5451A is designed to accommodate common mode + signal levels from VA- to VA+. Figure 2 illustrates the
+3 V
VA + R EF IN O ption al E xte rn al Re fe ren ce R E FO U T
VD+
1 .2 V
V
+ PHA SE
V IN 1+, V IN2 +, or V IN 3+
VIN 1 -, VIN2 -, o r V IN3-
IIN1 +, IIN 2 +, o r IIN 3+ I P HAS E
N O T E : Current input channels actually measure voltage.
IIN 1 -, I IN 2 - , o r II N 3 -
AG ND
VA -
DG ND
-2 V
Figure 2. Typical Connection Diagram DS635PP1 9
CS5451A
CS5451A typical inputs and power supply connections. This filter samples the modulator bit stream at XIN/8 Hz and decimates to XIN/2048 Hz. If the OWRS pin is set to logic high, then the transfer function is
3.2
Performing Measurements
The converter outputs are transferred in 16-bit signed (two's complement) data formats as a percentage of full scale. Table 1 below illustrates the ideal relationship between the differential voltage presented to any one of the input channels and the corresponding output code. Note that for the current channels, the state of the GAIN input pin is assumed to driven low such that the PGA gain on the current channels is 1x. If the PGA gain of the current channels is set to 20x, a +40 mV differential voltage is presented across any pair of "IINk+" and "IINk-" pins (k = 1, 2, 3) would cause a (nominal) output code of 32767.
Differential Input Output Code Output Code Voltage (mV) (hexadecimal) (decimal) +800 0.0122 to 0.0366 -0.0122 to 0.0122 -0.0122 to -0.0366 -800 7FFF 0001 0000 FFFF 8000 32767 1 0 -1 -32768
1 - z - 128 3 H ( z ) = --------------------- -1 1-z
The above filter samples the modulator bit stream at XIN/8 Hz and decimates to XIN/1024 Hz.
3.4
Serial Interface
The CS5451A communicates with a target device via a master serial data output port. Output data is provided on the SDO output synchronous with the SCLK output. A third output, FSO, is a framing signal used to signal the start of output data. These three outputs will be driven as long as the SE (serial enable) input is held high. Otherwise, these outputs will be high impedance. Data out (SDO) changes as a result of SCLK falling, and always outputs valid data with SCLK rising. When data is being transferred, the SCLK frequency is either 1/8 of the XIN input frequency (when OWRS is held low) or 1/4 of the XIN input frequency (when OWRS is held high). Any other time, SCLK is held low. (See Figures 3 and 4.) The framing signal (FSO) output is normally low, but produces a high level pulse lasting one SCLK period when the instantaneous voltage/current data samples are about to be transmitted out of the serial
Table 1. Nominal Relationship for Differential Input Voltage vs. Output Code, for all channels. (Assume PGA gain is set to 1x.)
3.3
High Rate Digital Filters
If the OWRS pin is set to logic low, the high-rate filters are implemented as fixed sinc3 filters with the following transfer function:
1 - z - 256 3 H ( z ) = --------------------- 1 - z-1
10
DS635PP1
CS5451A
96 SCLKs
SCLK
... ...
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 7 65 4 3 2 1 0 15 14
... ...
... 3 2 1 0
FSO
SDO
[ Undefined ] Channel 1 ( V ) Channel 1 ( I )
...
...
[ Undefined ]
Ch. 2 ( V ) ... Ch. 2 ( I ) ... Ch. 3 ( V ) ... Ch. 3 ( I )
Figure 4. Close-up of One Data Frame
interface (after each A/D conversion cycle). Note: SCLK is not active during FSO high. For 96 SCLK periods after FSO falls, SCLK is active and SDO produces valid output. Six channels of 16 bit data are output, MSB first. Voltage and current measurements are output (in that order) for three phases. SCLK will then be held low until the next sample period.
A hardware reset is initiated when the RESET pin is forced low with a minimum pulse width of 50 ns.
3.6
Analog Inputs
3.5
System Initialization
The analog inputs of the CS5451A are bipolar voltage inputs: Three voltage channel inputs VIN(1-3) and three current channel inputs IIN(1-3). The CS5451A accommodates a full scale range of 80 mVP-P or 1. 6VP-P on the Current Channels and 1.6 VP-P on the Voltage Channels.
When power to the CS5451A is applied, the chip must be held in a reset condition using the RESET input.
3.7
Voltage Reference
The CS5451A is specified for operation with a +1.2 V reference between the VREFIN and AGND pins. The converter includes an internal 1.2 V reference
SCLK
96 SCLKs
FSO
Each data segment is 16 bits long.
SDO
Channel 1 V Channel 1 I Channel 2 V Channel 3 I Channel 3 V Channel 2 I
Figure 3. Serial Port Data Transfer
DS635PP1
11
CS5451A
(50 ppm/C drift) that can be used by connecting the VREFOUT pin to the VREFIN pin of the device. If higher accuracy/stability is required, an external reference can be used.
CPD AG N D
3.8
Power Supply
B AT 8 5 D1
40 n F C1 D2 B A T 85
The low, stable analog power consumption and superior supply rejection of the CS5451A allow for the use of a simple charge-pump negative supply generator. The use of a negative supply alleviates the need for level shifting of the analog inputs. The CPD pin and capacitor C1 provide the necessary analog supply current as shown in Figure 5. The Schottky diodes D1 and D2 are chosen for their low forward voltages and high-speed capabilities. The capacitor C2 provides the required charge storage and bypassing of the negative supply. The CPD output signal provides the charge pump driver signal. The frequency of the charge pump driver signal is synchronous to XIN. The nominal average frequency is 1 MHz. The level on the VA- pin is fed back internally so that the CPD output will regulate the VA- level to -2/3 of VA+ level. Note the value of C1 in Figure 5. The 40 nF value is recommended when the input frequency presented to the XIN pin is 4.00 MHz. If the user decides to use an XIN frequency that is significantly different than 4.00 MHz (if the XIN frequency is increased/decreased by more than 5% of 4.00 MHz, then it is recommended that the user should alter the value of C1. The percentage change in the value of C1 (with respect to a reference value of 40 nF) should be inversely proportional to the percentage change in the XIN frequency. For example, if the XIN frequency is increased from 4.00 MHz to
V A-
C2 1 F
Figure 5. Generating VA- with a Charge Pump
4.5 MHz, this represents a percentage increase of 12.5%. Therefore, the value of C1 should be reduced by 12.5%, making the new value for C1 to be 35 nF. For more information about the operation of this type of charge pump circuit, the reader can refer to Cirrus Logic, Inc.'s application note AN152: Using the CS5521/24/28, and CS5525/26 Charge Pump Drive for External Loads.
3.9
PCB Layout
For optimal performance, the CS5451A should be placed entirely over an analog ground plane with both the VA- and DGND pins of the device connected to the analog plane. Place the analog-digital plane split immediately adjacent to the digital portion of the chip.
Note: Refer to the CDB5451 Evaluation Board for suggested layout details and Applications Note 18 for more detailed layout guidelines. Before layout, please call for our Free Schematic Review Service.
12
DS635PP1
CS5451A
4. PACKAGE DIMENSIONS
28L SSOP PACKAGE DRAWING
N
D
E11 A2 A1 A
E
L
e
b
2
END VIEW
SIDE VIEW
123
SEATING PLANE
TOP VIEW
INCHES DIM A A1 A2 b D E E1 e L MIN -0.002 0.064 0.009 0.390 0.291 0.197 0.022 0.025 0 NOM -0.006 0.069 -0.4015 0.307 0.209 0.026 0.0354 4 MAX 0.084 0.010 0.074 0.015 0.413 0.323 0.220 0.030 0.041 8 MIN -0.05 1.62 0.22 9.90 7.40 5.00 0.55 0.63 0
MILLIMETERS NOM -0.13 1.75 -10.20 7.80 5.30 0.65 0.90 4 MAX 2.13 0.25 1.88 0.38 10.50 8.20 5.60 0.75 1.03 8
NOTE
2,3 1 1
JEDEC #: MO-150 Notes: 1. "D" and "E1" are reference datums and do not included mold flash or protrusions, but do include mold mismatch and are measured at the parting line, mold flash or protrusions shall not exceed 0.20 mm per side. 2. Dimension "b" does not include dambar protrusion/intrusion. Allowable dambar protrusion shall be 0.13 mm total in excess of "b" dimension at maximum material condition. Dambar intrusion shall not reduce dimension "b" by more than 0.0 7mm at least material condition. 3. These dimensions apply to the flat section of the lead between 0.10 a nd 0.25mm from lead tips.
DS635PP1
13
CS5451A
5. REVISIONS
Date July 2003 Initial Release Changes A1 PP1
Revision
13 October 2003 Initial release for Preliminary Product Information
Contacting Cirrus Logic Support
F or all p rod uct q ue stio ns an d inq uirie s c ont act a Cir r us Logic Sal es Re pres e n t ative. T o fin d the on e ne a re st to yo u g o to www.cirrus.com
IMPORTANT NOTICE "Preliminary" product information describes products that are in production, but for which full characterization data is not yet available. Cirrus Logic, Inc. and its subsidiaries ("Cirrus") believe that the information contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided "AS IS" without warranty of any kind (express or implied). Customers are advised to obtain the latest version ofrelevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the te rms and conditi of sale supplied at the time of order ons acknowledgment, including those pertaining to warranty, patent infringement, and lim itation of liability. No responsibility is assumed by Cirrus for the use of this information, including use of this information as the basis for manufacture or sale of any items, or for infringement of patents or other rights of third parties. This document is the property of Cirrus and by furnishing this information, Cirrus grants no license, express or implied under any pa tents, mask work rights, copyrights, trademarks, trade secrets or other intellectual property rights. Cirrus owns the copyrights associated with the infor mation cont ained herein and gives consent for copies to be made of the infor mation only for use within your organization with respect to Cirrus integrated circuits or other p roducts of Cirrus. This consent does not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale. An export permit needs to be obtained from the com petent authorities of the Japanese Government if any of the products or techno logies described in this material and controlled under the "Foreign Exchange and Foreign Trade Law" is to be exported or taken out of Japan. An export license and/or quota needs to be obtained from the competent authorities of the Chinese Government if any of the products or technologies described in this material is su bject to the PRC Foreign Trade Law and is to be exported or taken out of the PRC. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE ("CRITICAL APPLICATIONS"). CIRRUS PRODUCTS ARE NOT DESIGNED, AUTHORIZED OR WARRANTED FOR USE IN AIRCRAFT SYSTEMS, M ILITARY APPLICATIONS, PRODUCTS SURGICALLY IMPLANTED INTO THE BODY, LIFE SUPPORT PRODUCTS OR OTHER CRITICAL APPLICATIONS (INCLUDING MEDICAL DEVICES, AIRCRAFT SYSTEMS OR COMPONENTS AND PERSONAL OR AUTOMOTIVE SAFETY OR SECURITY DEVICES). INCLUSION OF CIRRUS PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTO MER'S RISK AND CIRRUS DISCLAIMS AND MAKES NO WARRANTY, EXPRESS, STATUTORY OR IMPLIED, INCLUDING THE IMPLIED WARRANTIES OF M ERCHANTABILITY AND FITNESS FOR PARTICULAR PURPOSE, WITH REGARD TO ANY CIRRUS PRODUCT THAT IS USED IN SUCH A MANNER. IF THE CUSTOMER OR CUSTOM ER'S CUSTOMER USES OR PERMITS THE USE OF CIRRUS PRODUCTS IN CRITICAL APPLICATIONS, CUSTOMER AGREES, BY SUCH USE, TO FULLY INDEMNIFY CIRRUS, ITS OFFICERS, DIRECTORS, EMPLOYEES, DISTRIBUTORS AND OTHER AGENTS FROM ANY AND ALL LIABILITY, INCLUDING ATTORNEYS' FEES AND COSTS, THAT MAY RESULT FROM OR ARISE IN CONNECTION WITH THESE USES. Cirrus Logic, Cirrus, and the Cirrus Logic logo designs are trademarks of Cirrus Logic, Inc. All other brand and product names in this document m ay be trademarks or service marks of their respective owners.
14
DS635PP1

▲Up To Search▲

Price & Availability of CS5451A

	To Download CS5451A Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .